Not known Factual Statements About Anti-Tamper Digital Clocks
Not known Factual Statements About Anti-Tamper Digital Clocks
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30. An apparatus for detecting voltage tampering, comprising: signifies for delivering a gradual-condition monotone signal during an Examine time frame;
The strategy with the invention could be executed based on combinatorial logic employing static CMOS, which is pretty inexpensive primarily based the processor's present circuit integration. Detection compensation for process, voltage, and temperature variants of your delay lines, might be realized by adapting the number of hold off strains and multi-frequency program assistance.
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23. A method for detecting voltage tampering, comprising: offering a plurality of resettable delay line segments, wherein resettable delay line segments between a resettable delay line section linked to a minimum hold off time here as well as a resettable delay line phase connected to a most delay time are Every single connected to discretely raising delay instances;
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eight. An equipment for detecting clock tampering, comprising: suggests for delivering a monotone signal during a clock Examine time frame associated with a clock;
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The monotone 0 to 1 transition may be attained by introducing reset operators. Just about every reset operator could reset the respective delay line in the sensing circuit in the course of the reset section to a recognised condition unbiased of any set up-violations, even though the circuit senses during the evaluation phase. With no reset operators, the sensing circuit that detects slower than anticipated frequencies might be in an unknown condition.
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One more aspect of the invention might reside within an equipment for detecting voltage tampering, comprising: means for delivering a monotone signal in the course of an Appraise time; means for delaying the monotone signal utilizing a plurality of resettable hold off line segments to produce a respective plurality of delayed monotone alerts getting discretely expanding hold off periods in between a bare minimum delay time and a highest delay time; and signifies for using the clock to set off an evaluate circuit that uses the plurality of delayed monotone alerts to detect a voltage fault.
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